These modules utilize specialized stacks of 3D NAND—a type of non-volatile memory that retains data without power—to offer up to 512GB of capacity in a single package.
This standard is significant for the future of AI infrastructure because it provides a bridge between traditional storage and expensive High Bandwidth Memory (HBM).
While HBM currently powers the most advanced AI chips, its capacity is limited.
HBF offers a way to store significantly more data closer to the processor, which is essential for AI inference, the stage where a trained model processes new information to make predictions.
By offering up to eight times the capacity of upcoming HBM4 stacks, HBF could allow data centers to run massive AI models more efficiently.
To ensure broad compatibility, the technology adopts the Universal Chiplet Interconnect Express (UCIe) standard, an industry-wide protocol that allows different components to work together seamlessly within a single chip package.
Although the specification is now public, widespread industry adoption remains the next major hurdle.
Companies like Google and Tenstorrent have expressed interest in the consortium, but the technology’s ultimate success will depend on whether other major hardware manufacturers integrate the new interface into their future business roadmaps.